FIG. 1(A) is a cross sectional view showing a simplified integrated circuit (IC) device 100-1. IC device 100-1 includes numerous transistors 110 that are fabricated on a substrate 120, such as a silicon wafer. Transistors 110 include source regions 112 and drain regions 114 diffused into substrate 120, and a gate structure 116 formed over a channel separating source region 112 and drain region 114. Formed over transistors 110 is a conductor region 130 including alternating layers of metal lines 133 and insulating material 136 (such as silicon dioxide). Metal lines 133 are used to transmit signals between the various transistors 110 of IC device 100-1.
Programmable logic devices (PLDs) are a type of IC device that include logic resources and associated interconnect resources that are selectively controlled to implement user-defined logic operations (that is, a user's circuit design). In SRAM-based PLDs, the interconnect resources typically include pass transistors whose gates are controlled by SRAM cells to connect interconnect line segments such that signal paths are formed in accordance with a logic operation. These SRAM cells are often programmed once during a configuration phase, and then remain turned on or turned off (i.e., static) during subsequent operational phases.
FIG. 1(B) is a simplified perspective view depicting portions of the interconnect resources of a PLD 100-2. Like IC 100-1 (FIG. 1(A)), PLD 100-2 includes transistors (not shown) formed on a substrate 120 under a conductor region 130 made up, for example, of layers of metal lines and insulation material (not shown). Some of the transistors of PLD 100-2 are utilized to form SRAM cells 140-1 through 140-3 (each illustrated as two inverters connected in a loop) that store configuration data used to control an associated pass transistor 150-1 through 150-3. Pass transistors 150-1 through 150-3 are connected between associated pairs of interconnect line segments 160-1 through 160-6. As mentioned above, interconnect line segments 160-1 through 160-6 are connected, for example, to logic resources (not shown) of PLD 100-2. To implement a particular logic operation, a user configures SRAM cells 140-1 through 140-3 such that signals are transmitted (or not transmitted) based on the state (open or closed) of pass transistors 150-1 through 150-3.
Electron beam deflection devices have been used for several years to debug (test) ICs during development. These devices typically include an electron beam emission device, an imaging device for directing the electron beam to a point on an IC-under-test, and a reception device for measuring the energy distribution of electrons leaving the point of the IC-under-test in response to electron beam bombardment. Electron beam deflection devices are able to view (measure) the presence or absence of an alternating signal at a selected point on the surface of the IC-under-test by detecting fluctuations in the energy distribution of electrons reflected from the selected point. Therefore, a test engineer is able to debug (test) an IC by applying predetermined input signals and viewing (measuring) the resulting currents through conductors exposed on a surface of the IC.
There are several problems associated with the use of electron beam deflection devices to troubleshoot ICs after fabrication. A first problem arises because most of the conductors of the IC (i.e., interconnect line segments 160-1 through 160-6 of a PLD 100-2 shown in FIG. 1(B)) are obscured by one or more insulation/metal lines associated with conductor region 130 (see FIG. 1(A)). A second problem is that several of the conductors of an IC (such as the SRAM cells 140-1 through 140-3 shown in FIG. 1(B)) are maintained at a static signal level (i.e., high or low). As mentioned above, electron beam deflection devices detect alternating signals; they are unable to detect these static signals.
What is needed is a method and structure for testing static signals generated at points buried within ICs that can be performed using electron beam deflection devices.